1. Field of the Invention
Generally, the present disclosure relates to the formation of integrated circuits, and, more particularly, to the formation of a dielectric interlayer between and over circuit elements including closely spaced lines, such as gate electrodes, polysilicon interconnect lines and the like.
2. Description of the Related Art
During the fabrication of integrated circuits, a large number of circuit elements are formed on a given chip area according to a specified circuit layout. Generally, a plurality of process technologies are currently practiced, wherein, for complex circuitry, such as microprocessors, storage chips and the like, MOS technology based on silicon is currently the most promising approach due to the superior characteristics in view of operating speed and/or power consumption and/or cost effectiveness. During the fabrication of complex integrated circuits using MOS technology, millions of transistors, i.e., N-channel transistors and/or P-channel transistors, are formed on a substrate including a crystalline semiconductor layer, such as a silicon-based layer. A MOS transistor, irrespective of whether an N-channel transistor or a P-channel transistor is considered, comprises so-called PN junctions that are formed by an interface of highly doped drain and source regions with a lightly doped channel region disposed between the drain region and the source region. The conductivity of the channel region, i.e., the drive current capability of the conductive channel, is controlled by a gate electrode that comprises a line-like portion and is formed above the channel region and separated therefrom by a thin insulating layer.
Typically, the circuit elements, such as the MOS transistors, capacitors, resistors and the like, are formed in a common layer, which will be referred to hereinafter as a device layer, whereas the “wiring,” i.e., the electrical connection of circuit elements according to the circuit design, may be accomplished only to a certain degree by means of polysilicon lines and the like within the device layer so that one or more additional “wiring” layers formed over the device layer may be required. These wiring layers include metal lines embedded into an appropriate dielectric material, such as silicon dioxide, silicon nitride and the like, or, in advanced devices, low-k materials having a permittivity of 3.0 or less are used. The metal lines and the surrounding dielectric material will be referred to hereinafter as a metallization layer. Between two stacked adjacent metallization layers and also between the device layer and the first metallization layer, respective dielectric interlayers are formed through which metal-filled openings are formed to establish the electrical connection between metal lines or between circuit elements and metal lines. In typical applications, the dielectric interlayer separating the device layer from the first metallization layer is essentially formed from silicon dioxide that is deposited above a dielectric etch stop layer by well-established plasma enhanced chemical vapor deposition (PECVD) techniques, which enable the formation of a smooth and dense silicon dioxide film with sufficient conformality at moderately high deposition rates. Due to the continuous device scaling resulting in gate lengths of MOS transistors on the order of 50 nm or less, the distances between neighboring circuit elements, such as polysilicon lines, gate electrodes and the like, are also reduced and have now reached, in modern CPUs, approximately 200 nm and less, which translates into approximately 100 nm or less for the space width between the densely packed polysilicon lines. It turns out, however, that the gap-fill capabilities of well-established high rate PECVD techniques for the deposition of silicon nitride, which is frequently used as material for the etch stop layer, and silicon dioxide, which is often used as interlayer dielectric, may no longer suffice to reliably form a dielectric interlayer, as will be described in more detail with reference to FIGS. 1a-1b. 
FIG. 1a schematically illustrates a cross-sectional view of a semiconductor device comprising a plurality of transistor elements wherein, for convenience, only two transistor elements 150A, 150B are shown. The transistors 150A, 150B may be formed in and above a semiconductor layer 102, for instance a silicon-containing semiconductor material, or any other appropriate material for forming therein appropriately shaped dopant profiles as may be required for sophisticated transistor elements and other circuit features, such as capacitors and the like. The semiconductor layer 102 is formed above a substrate 101 which may represent a semiconductor material, such as a silicon material and the like. The semiconductor layer 102 and the substrate 101 may represent a “bulk” configuration in which the substrate 101 may be comprised of substantially the same crystalline material as the semiconductor layer 102. In other cases, the substrate 101 and the semiconductor layer 102 may represent a silicon-on-insulator (SOI) configuration, wherein at least a portion of the substrate 101 may comprise an insulating material, such as a silicon dioxide material, on which is formed the semiconductor layer 102. Moreover, in the manufacturing stage shown, the transistors 150A, 150B may each comprise a gate electrode structure 152 comprised of an electrode portion 153, which may be comprised of a suitable electrode material, such as polysilicon. Furthermore, the gate electrode structures 152 may comprise a gate insulation layer 154 including any appropriate material composition, such as silicon dioxide, silicon nitride, high-k dielectric materials in sophisticated applications and the like. Furthermore, a sidewall spacer structure 156 may be provided on sidewalls of the gate electrode structure 152, wherein the spacer structure 156 may comprise two or more individual spacer elements, possibly in combination with respective etch stop materials, as is well known in the art. Furthermore, respective drain and source regions 151 are provided in the semiconductor layer 102 with a suitable vertical and lateral profile for obtaining the desired transistor characteristics.
The semiconductor device 100 as shown in FIG. 1a may be formed on the basis of well-established conventional process strategies, which may include the following processes. After forming appropriate isolation structures (not shown), which may define respective active regions in the semiconductor layer 102 to form therein circuit elements, such as the transistors 150A, 150B, the gate insulation layer 154 may be formed, for instance, by oxidation and/or deposition techniques, in order to obtain a desired thickness and material composition. Thereafter, a gate electrode material, such as polysilicon, may be deposited, for instance, by low pressure chemical vapor deposition (LPCVD) techniques, wherein a thickness of the polysilicon material may be selected in accordance with process requirements for the device 100. That is, in sophisticated applications, a thickness of the polysilicon material, which may thus determine the finally obtained height 152H of the gate electrode structure 152, may be selected such that, on the one hand, the functionality of the gate electrode structure 152 may be achieved and, on the other hand, in view of acting as an efficient implantation mask during the definition of the drain and source regions 151, a sufficient shielding effect is achieved to suppress the introduction of dopants in a channel region 155. Thus, after the deposition of the electrode material with the required thickness 152H, sophisticated lithography and patterning process are performed in order to define the lateral size of the gate electrode structure 152. Thereafter, a first portion of the drain and source regions 151 may be formed, for instance, on the basis of a respective offset spacer (not shown) by ion implantation, wherein, typically, a shallow dopant profile is to be established while using the gate electrode structure 152, possibly in combination with any offset spacers, as an efficient implantation mask. Next, the spacer structure 156 may be formed using well-established deposition and etch techniques to obtain the desired lateral shielding effect of the gate electrode structure 152 in combination with the spacer structure 156. Thereafter, an implantation process 103 is performed with appropriately selected process parameters, such as implantation energy and dose, to position a required dopant concentration at a desired depth within the semiconductor layer 102, while the spacer structure 156 defines a lateral profile of the dopant concentration. Furthermore, during the implantation process 103, penetration of dopant species into the channel region 155, which is substantially positioned below the gate electrode structure 152, may have to be avoided since any additional dopant species positioned therein may significantly alter the finally obtained transistor characteristics, for instance, in terms of threshold voltage, control of short channel effects and the like. Thus, the height 152H and the gate electrode structure 152 is selected such that the implantation blocking capability of the polysilicon portion 153 is sufficient to substantially avoid the penetration of the gate insulation layer 154 and the underlying channel region 155. After the implantation process 103, an appropriately designed anneal process may be performed in order to activate the dopants in the drain and source regions 151 and also re-crystallize implantation-induced damage in the semiconductor layer 102.
FIG. 1b schematically illustrates the semiconductor device 100 in a further advanced manufacturing stage, in which metal silicide regions 157 may be formed in the drain and source regions 151 and also in the polysilicon electrode portions 153. Additionally, a first portion of an interlayer dielectric material, for instance, in the form of a silicon nitride layer 104, is provided above the first and second transistors 150A, 150B. As previously explained, in advanced semiconductor devices, a spacing 105 between closely spaced circuit elements, such as the transistors 150A, 150B may be reduced with the advance to a new technology standard, which may thus require enhanced gap-filling capabilities of deposition processes for forming an interlayer dielectric material, such as the silicon nitride layer 104. Consequently, after the forming of the metal silicide regions 157, which may be accomplished on the basis of well-established techniques, typically a PECVD process is performed to deposit the silicon nitride material 104, wherein, however, the moderately high aspect ratio defined by the distance 105 and the height 152H of the gate electrode structure 152 may result in irregularities, for instance, in the form of voids 104A, which may be caused by the non-sufficient conformal deposition capabilities of the respective PECVD process. The irregularities 104A may thus result in process non-uniformities during the further deposition of a further interlayer dielectric material, such as a silicon dioxide material, and may also result in contact failures, when forming respective openings for contacts in order to connect the transistors 150A, 150B with a metallization level to be formed above the transistors 150A, 150B. Since the layer 104 may be used as an etch stop layer and, in sophisticated applications, may also be used as a strain-inducing source as silicon nitride may be deposited with high internal compressive and tensile strain, an arbitrary reduction of the layer thickness of the layer 104 in view of enhancing the conformal deposition behavior may be less than desirable.
The present disclosure is directed to various methods and devices that may avoid, or at least reduce, the effects of one or more of the problems identified above.